The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely sophisticated devices, and computer systems may be found in many different settings. Computer systems typically include a combination of hardware (such as semiconductors, integrated circuits, programmable logic devices, programmable gate arrays, and circuit boards) and software, also known as computer programs.
The design of circuits is complicated due to the high speed performance requirements typical of computer system hardware. In order to meet these requirements, analysis of the circuit design is necessary prior to building hardware, in order to ensure proper high-speed propagation and performance. This early analysis of the design facilitates early design trade-offs that ultimately reduce the development cycle time of the product that includes the circuit and the number of versions of the hardware that are necessary to meet product requirements. Topology checking tools are used during the early analysis to help determine proper length, placement, and routing of the high speed signals used in the circuit to meet performance requirements. Such tools involve placing constraints on the topology of signal nets and then checking these constraints during physical design. This process requires users to write topology rules describing signal design and interconnects across boundaries of packages on which the circuit is located.
For a circuit that has signaling across multiple package boundaries, a user must write rules for each package that the signals cross. In a typical system, this involves manually writing topology rules and then managing the checking of these constraints on each package for each signal, which is cumbersome and quickly becomes impossible for a system that has thousands of nets across multiple packages.
What is needed is a technique that generates topology rules and handles system level nets across package boundaries.